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MYSON TECHNOLOGY
MTD214
Ethernet Encoder/Decoder and 10BaseT Transceiver with Built-in Waveform Shaper
FEATURES
* * * * * * * * * *
Compatible with IEEE 802.3 standards. Built-in UTP output waveform shaping function. Selectable media interface and auto-detection functions. Automatic polarity detection and correction. Link status output. Heartbeat disable/enable selection. Support full-duplex operation. Standard 802.3 AUI interface. Selectable controller interface. Low power consumption.
GENERAL DESCRIPTION
MTD214 contains integrated functions of the Ethernet encoder/decoder and UTP/AUI interface. The encoder/decoder conforms to IEEE 802.3 protocol and performance requirements while also retaining compatibility with most popular network controllers. The UTP transceiver has a built-in waveform shaping function thus eliminating the requirement of an external filter. The transceiver also contains the functions of automatic media selection and polarity correction. MTD214 is available in 28-pin plastic DIP (600mil) or SOJ (300mil) packages.
BLOCK DIAGRAM
VCO/PLL
2
AUI
2 2
DIP/DIN CIP/CIN DOP/DON
CRS RXC RXD COL/HBE
MANCHESTER DECODER
UTP RECEIVE
2
TPIP/TPIN
TXE TXD TXC
MANCHESTER ENCODER
LINK TEST/ JABBER
LTE/LS
NIS CIS FDX
CONTROL
UTP TRANSMIT
X1 X2
REFERENCE CLOCK
OUTPUT DRIVER
2
TPOP/ TPON
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product. MTD214 Revision 1.4 1205/1997 1/11
MYSON TECHNOLOGY
1.0 CONNECTION DIAGRAM
MTD214
2.0 PIN DESCRIPTIONS
Name GNDA VDDA COL/HBE I/O P P I/O Pin # 1 2 3 Descriptions Ground for analog and internal circuits. +5V (+/-5%) supply for internal circuits. Collision detection output connecting to the network controller. This pin is also an input pin that determines the heartbeat function. During reset period, COL output is disabled, and input is latched to control the heartbeat function. After reset, COL is asserted when a collision is sensed on the network, during heartbeat period or jabber condition. Receives data output connecting to the network controller. RXD is the decoded NRZ data from the network. Carrier sense output connecting to the network controller. CRS is asserted when there is activity on the media, and is de-asserted by the end of the packet condition on the media. It is also deasserted if loss of SYNC condition occurs during the reception of the packets. Receives clock output connecting to the network controller. RXC is derived from the Manchester data on the received data. In NS/AMD mode, it is active only during packet reception. In Intel/AT&T mode, it is continuous following the TXC clocks during idle period and switched to the received clocks as the packet arrives.
MTD214 Revision 1.4 12/05/1997 2/11
RXD CRS
O O
4 5
RXC
O
6
MYSON TECHNOLOGY
LTE/LS I/O 7
MTD214
CIS NIS
I I
8 9
X1/X2
I
10,11
TXD TXC TXE FDX
I O l I
12 13 14 15
GNDO TPOP/TPON
P O
17 18,16
GNDD VDDD DOP/DON
P P O
19 20 22,21
CIP/CIN
I
23,24
Test enabler and status links. This is a dual-purpose pin. It is an input that occurs during the power-on reset period. If MTD214 senses it is high during reset, MTD214 enables the link test function of the on-chip UTP transceiver and outputs the link status through this pin. To disable the link test function, this pin should be forced below 1.5 V during reset. Note that MTD214 always outputs the link pulses independent of the link test. Controller interface selection. This pin selects the signal format of the ENDEC output. If it is high, the format conforms to the Intel/AT&T controller. If it is low, it conforms to NS/AMD format. Media interface selection. This pin selects the network media. If it is high, the on-chip UTP transceiver is selected. If it is low, AUI is selected. It is also combined with the FDX pin to define the loopback test mode. Please see the functional description for the mode table. Crystal oscillator. A 20MHz-30pF with 100ppm accuracy crystal should be mounted between these 2 pins as well as two 30pF +/- 5% capacitors connecting each pin to ground. If an external clock source is used, it should be applied through X1 and allow X2 to be grounded. Transmitted data input connected to the network controller. The data is in NRZ format and is gated by the TXE signal. Transmitted clock output connected to the network controller. This is a 10MHz clock used to synchronize TXE and TXD. Transmitted enabler input connected to the network controller. This signal is used by MTD214 to gate the TXD input for packet transmission. Full duplex mode selection input. When this pin is low, half duplex and normal Ethernet operation is selected. When this pin is high, full duplex mode operation is enabled. In this mode, the collision status reporting is disabled, but heartbeat and jabber conditions are still reported on the COL pin. Since full duplex mode can be implemented in UTP media only when MTD214 is in auto media selection mode, AUI selection precedes the priority of full duplex mode. This pin is also combined with the NIS pin to define various testing modes of MTD214. Ground for UTP output transmitter. UTP transmitted output connected to an output transformer that couples with the UTP cable. The transformer should have an inductance of 100 to 200 uH and 1:1 turn ratio. Two 50-Ohm load resistors should also connect each output to VDD as load resistors. It is also recommended that a 100pF capacitor be connected to this pin from ground to remove any spurious noise. Ground for UTP output transmitter and AUI buffer. +5 V supply for AUI buffer. Data output for AUI interface. This differential signal should drive an equivalent load of 39 Ohm. Typically an external 78 Ohm connected across these 2 pins and the equivalent remote AUI load together are used to ensure proper amplitude. The AUI interface should be transformer-coupled. Collision input for AUI interface. This differential signal is coupled through the transformer. An external bias of 2.5V should be applied to these 2 pins.
MTD214 Revision 1.4 12/05/1997 3/11
MYSON TECHNOLOGY
DIP/DIN TPIP/TPIN I I 25,26 27,28
MTD214
Data input for AUI interface. This differential signal is coupled through the transformer. An external bias of 2.5V should be applied to these 2 pins. UTP receiving input. This differential signal is connected to the UTP receiving pair through the isolation transformer. An external bias of 2.5V should be applied to these 2 pins.
3.0 FUNCTIONAL DESCRIPTION
3.1 Manchester Decoder and PLL The Manchester decoder uses a PLL to extract the clock and NRZ data from the received Manchester signals. The PLL is locked to the internally generated 5MHz clocks during idle time and switched to the incoming data at the start of the packet detection. The decoder also detects the IDL condition of the incoming data by switching off CRS whenever the data stays unchanged longer than 125 nsec. 3.2 Manchester Encoder The Manchester encoder receives the NRZ data from the controller and converts it into Manchester format using the internal 20MHz clocks. TXD and TXE must be synchronized by TXC. The encoder also guarantees that a low transition occurs first at the start of the packet and appends the IDL at the end of the transmitted data. 3.3 Reference and Clock An internal bandgap circuit is used to generate all necessary reference voltages and currents. The on-chip crystal oscillator is used to generate 20MHz reference clocks for the internal circuits. For precision clock generation, a 20MHz-30 100ppm crystal should be used. And two 30pF load capacitors should be connected from X1 and X2 to ground, respectively. If an external clock source is used, it should be applied to X1 while X2 is grounded. 3.4 Control Function This block controls the operating mode of MTD214. The CIS pin controls the type of controller interface. When CIS is high, MTD214 is in Intel/AT&T mode; when CIS is low, MTD214 is in NS/AMD mode. Do not allow this pin to float. NIS and FDX pins determine the operation mode according to the following table: FDX 0 0 0 1 1 1 F NIS 0 1 F 0 1 F X MODE Half Half Half Loopback Full Full/Half Test Mode MEDIA AUI UTP Auto detect N/A UTP Auto UTP/AUI
Note that full duplex mode is meaningful only if the media selection is UTP. Thus if MTD214 is configured as auto media switching, the full duplex is switched back to half duplex if AUI is selected. Also if the link test function is disabled (LTE=0), MTD214 assumes that the link test pass state and UTP are always selected if configured in auto detection mode. In full duplex mode, collision reporting is disabled and internal loopback of UTP transmission data is also inhibited. However, heartbeat and jabber functions of the on-chip UTP transceiver are still effective. 3.5 UTP Receiving A low-pass filter is used to filter the noise in the received UTP differential signals. The common-mode level of the differential signal is extracted and is used for DC squelch circuits. AC squelch circuits reject any single
MTD214 Revision 1.4 12/05/1997 4/11
MYSON TECHNOLOGY
MTD214
cycle signals between 3MHz and 15 MHz as well as continuous signals below 2.5MHz. The squelch circuit also recognizes the link pulses. Once the squelch is off, the differential signal is amplified to logic levels. There is no internal bias of TPIP and TPIN signals; an external bias (2.5V) should be applied to these inputs through the termination resistors. 3.6 Link Test and Jabber Logic The link test circuit performs the necessary link test functions specified by IEEE 802.3. The link test function is enabled when LTE/LS is sampled high during reset period. If the link test function is enabled, the LTE/LS pin becomes an output that can drive the link LED display. To disable the link test function, LTE should be tied low. The link test function can be changed only by power-on and off. Note that if the link test is disabled, the generation of link pulses is not affected. The link test status is used to control the on-chip UTP transceiver and the media selection. If the link test fails, and auto detection mode is enabled, the media is set to AUI. The link test circuit also includes the polarity detection function. Detection is based on the polarity of received link pulses. If 8 consecutive reversed link pulses are received, the polarity is toggled. The jabber logic monitors the length of the continuous transmission time. If the transmission time exceeds the maximum jabber time, the transmission is disabled and COL is asserted to indicate the jabber status. In addition, the logic implements the heartbeat function. The heartbeat enable signal is latched during reset period from the COL pin. To enable the heartbeat function, an external pull-up resistor of 4.7K Ohms should be connected to the COL pin. To disable the heartbeat function, a pull-down resistor should be used. 3.7 UTP Transmission and Output Driver The UTP transmission circuit takes the Manchester decoded data and converts it into a coded format that meets IEEE 802.3-required transmission templates. The coded data is fed into an oversampling D/A and filters for waveform shaping. The output buffer of the transmitter is an open-drain type current source. The output voltage of the transmitter is developed on the external load resistors (50 Ohm) connected to the power supply. The output should be transformer-coupled to the UTP media. 3.8 AUI Interface The AUI interface consists of CI/DI squelch detection and receiving circuits, and a DO output driver. The CI/ DI inputs should be externally biased at 2.5V through the termination resistors, and transformer-coupled to the AUI media. The DO output is a push-pull driver. The output should have an equivalent load of 39 Ohm to ensure proper amplitude. AUI media is selected either by setting NIS low or in auto switching mode with link fail conditions.
4.0 ELECTRICAL CHARACTERISTICS
4.1 DC Characteristics Ta = 0C to 70 C, VDD = 5V +/- 5%, Vss = 0V Parameter Supply current Idle Traffic Input low voltage (digital inputs) Input high voltage (digital inputs) Input high current (digital inputs) Input low current (digital inputs) Output low voltage (digital outputs/w IOL=4mA) Output high voltage (digital outputs/w IOH=500uA) AUI output differential voltage (DOP,DON) AUI idle offset voltage AUI input squelch voltage Symbol Idd, idle Idd, traf VIL VIH IIH IIL VOL VOH VOD VAI VAS Min -0.3 2.4 3.0 +/-500 -175
5/11
Typ 20 30 0.5 3.5 0 -250
Max 30 40 0.8 Vdd+0.3 100 100 0.8 +/-1500 +/-40 -300
Unit mA mA V V uA uA V V mV mV mV
Note
1
2
MTD214 Revision 1.4 12/05/1997
MYSON TECHNOLOGY
(DIP,DIN,CIP,CIN) UTP input squelch voltage (TPIP,TPIP) Analog input common voltage (DIP,DIN,CIP,CIN,TPIP,TPIN) UTP peak output voltage (TPOP,TPON) 4.2 Switching Characteristics 4.2.1 TP Reception Timing Parameter TP active to CRS assertion TP active to RXC validation TP end of packet detection (from bit boundary) Symbol tTPVCSH tTPVRCH tTPHCSL Min 100 Typ 300 9 125 Max 350 11 170 VTS VAC VTO +/-200 1.5 +/-2.0 +/-250 2.5 +/-2.5 +/-300 3.5 +/-3.0
MTD214
mV V V 3
Unit ns BT ns
Note
RECEIVE START OF PACKET
RECEIVE END OF PACKET
TPI
Bit Boundary
IDL
CRS
tTPVCSH tTPHCSL
RXC
tTPVRCH
Figure 1. TP Reception Timing 4.2.2 TP Transmission Timing Parameter TXE to TP output TXE to CRS loopback TXE to RXC loopback TP end of packet IDL width Symbol tTNHPOX tTNHCSH tTNHRCC tPOHPOL Min 250 Typ 100 150 8 275 Max 150 200 10 300 Unit ns ns BT ns Note
MTD214 Revision 1.4 12/05/1997 6/11
MYSON TECHNOLOGY
TRANSMIT START OF PACKET
MTD214
TRANSMIT END OF PACKET
TXE
TPO
tTNHPOX
IDL
tPOHPOL
CRS
tTNHCSH
RXC
tTNHRCV
Fig ure 2. TP Transmission Timing
4.2.3 TP Collision Timing Parameter TPI to COL assertion TPI to COL de-assertion TXE to COL assertion TXE to COL de-assertion
TRANSMIT-RECEIVE COLLISION DETECTION
Symbol tTPVCLH tTPHCLL tTNHCLH tTNLCCL
Min -
Typ 300 125 125 350
Max 400 200 200 450
Unit ns ns ns ns
Note
RECEIVE-TRANSMIT COLLISION DETECTION
TXE
TPI
IDL
COL
tTPVCLH tTPHCLL tTNHCLH tCLHCLL tTNLCLL
Figure 3. TP Collision Timing 4.2.4 TP HBT and Jabber Timing Parameter Heartbeat delay Heartbeat duration Jabber turn-on time Jabber reset time
TXE
Symbol tTNLCLV tTNLCLL tTNHCJH tTNHCJL
Min 800 800 40 250
Typ 1000 1000 45 500
Max 1200 1200 55 750
Unit ns ns ms ms
Note
COL
tTNLCLV
tTNHCJH
tTNLCJL
TPO
Figure 4. TP HBT and Jabber Timing
MTD214 Revision 1.4 12/05/1997 7/11
MYSON TECHNOLOGY
4.2.5 AUI Reception Timing Parameter DI active to CRS assertion DI active to RXC validation DI end of packet detection (from bit boundary) Symbol tDIVCSH tDIVRCH tDIHCSL Min 100 Typ 40 4 125 Max 80 6 170
MTD214
Unit ns BT ns
Note
RECEIVE START OF PACKET
RECEIVE END OF PACKET
DI
Bit Boundary
IDL
CRS
tDIVCSH tDIHCSL
RXC
tDIVRCH
Figure 5. AUI Reception Timing 4.2.6 AUI Transmission Timing Parameter TXE to DO output DO end of packet IDL width Symbol tTNHDOX tDOHPOL Min 250 Typ 100 275 Max 150 300 Unit ns ns Note
TRANSMIT START OF PACKET
TRANSMIT END OF PACKET
TXE DO
tTNHDOX
IDL
tDOHDOL
Figure 6. AUI Transmission Timing 4.2.7 Local Loopback Timing Parameter TXE to CRS assertion TXE to RXC validation Symbol tTNHCSH tTNHRCV Min Typ 60 6 Max 100 8 Unit ns BT Note
MTD214 Revision 1.4 12/05/1997 8/11
MYSON TECHNOLOGY
TXE
MTD214
CRS
tTNHCSH
RXC
tTNHRCV
Figure 7. Local Loopback Timing 4.2.8 Controller Interface Timing (NS/AMD Mode) Parameter RXD setup to RXC rising RXD hold after RXC RXC low to CRS de-assertion TXE setup to TXC rising TXD setup to TXC rising TXE hold after TXC TXD hold after TXC
START OF PACKET
Symbol tRDVRCH tRCHRDH tRCLCSL tTNVTCH tTDVTCH tTCHTNH tTCHTDH
Min 40 30 0 30 30 0 0
Typ 55 45 20 -
Max 50 -
Unit ns ns ns ns ns ns ns
Note
END OF PACKET
RXC
CRS
tRCLCSL
RXD
tRDVRCH tRCHRDH
Receive
TXC
TXE
tTNVTCH tTCHTNH
TXD
tTDVTCH tTCHTDH
Transmit
Fig
ure 8. Controller Interface Timing (NS/AMD Mode)
MTD214 Revision 1.4 12/05/1997 9/11
MYSON TECHNOLOGY
4.2.9 Controller Interface Timing (Intel/AT&T Mode) Parameter RXC to CRS assertion RXD setup to RXC fall RXD hold after RXC RXC high to CRS de-assertion TXE setup to TXC fall TXD setup to TXC fall TXE hold after TXC TXD hold after TXC Symbol tRCLCSL tRDVRCL tRCLRDH tRCHCSH tTNVTCL tTDVTCL tTCLTNH tTCLTDH Min 0 40 30 0 30 30 0 0 Typ 70 55 45 20 Max 100 50 -
MTD214
Unit ns ns ns ns ns ns ns ns
END OF PACKET
Note
START OF PACKET
RXC
tRCLCSL
CRS
tRCHCSH
RXD
tRDVRCL tRCLRDH
TXC
TXE
tTNVTCL tTCLTNH
TXD
tTDVTCL tTCLTDH
Figure 9. Controller Interface Timing (Intel/AT&T Mode) 4.2.10 Specific Timing for RXC and TXC Parameter RXC low width RXC high width TXC low width TXC high width
RXC
tRCLRCH tRCHRCL
Symbol tRCLRCH tRCHRCL tTCLTCH tTCHTCL
Min 45 45 45 45
Typ 50 50 50 50
Max 55 55 55 55
Unit ns ns ns ns
Note
TXC
tTCLTCH tTCHTCL
MTD214 Revision 1.4 12/05/1997 10/11
MYSON TECHNOLOGY
Figure 10. Specific Timing for RXC and TXC
MTD214
5.0 APPLICATION CIRCUITS
Please see attachment.
6.0 PACKAGE DIMENSION
A. 600 MIL 28-PIN PDIP Unit: mil
1540 +/-10
6o +/-3o 5 ~7 612 +/-12 550 +/-4
o 0
650 +/-20
10
70 +/-4 50Typ. 18+/-2Typ. 2050 +/-10 7Typ. 1.778mm +/-0.127 35+/-5 100Min. 0.254mm (min.) 100Typ. 70 +/-4
B. 300 MIL 28-PIN SOJ UNIT: INCH
28 15 0.007~0.013 R0.030" 0.040"
0.300 +/-0.005 0.335 bsc
0.267
1 0.725+/-0.01
14 0.138 +/-0.01
0.082Min.
0.026"/0.032"
0.05" Max. 0.1 ref
0.018 +/-0.002 0.050 bsc 0.025" Min.
MTD214 Revision 1.4 12/05/1997 11/11

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